Along with the progressing micronization of semiconductor devices, there has arisen a problem that a leakage current increases while a transistor is off, because of a so called short channel effect caused by expansion of a depletion layer around a drain diffusion layer toward a channel. For restraining the short channel effect, up until now an LDD (Lightly Doped Drain) structure has popularly been utilized, whereby an offset gate layer having a lower impurity concentration is formed between a gate and a source or a drain so as to achieve an impurity concentration gradient, and in order to cope with a further micronization of semiconductor devices, a technique of forming a shallow source or drain region (hereinafter briefly referred to as a “source/drain region”) in the proximity of a surface of a semiconductor substrate is popularly adopted. FIGS. 10A through 10D are cross-sectional process drawings showing a method of manufacturing a conventional semiconductor device.
Initially, a method of manufacturing an ordinary MOS transistor provided with a LDD structure will be described referring to FIGS. 10A through 10D. Firstly an element isolation dielectric film 2 is formed on a semiconductor substrate 1 by LOCOS method or trench method as shown in FIG. 10A, for defining a field region where a MOS transistor is to be formed. Then a gate dielectric film 8 constituted of a silicon oxide layer is formed by thermal oxidation method or the like, after which a polysilicon is deposited by low-pressure (LP) CVD method etc., to thereby form a gate electrode 9 by a known photolithography or a dry etching technique.
Thereafter, as shown in FIG. 10B, an LDD region 7 is formed by ion implantation method utilizing the gate electrode 9 as a mask; specifically by implanting an N-type impurity such as a low-concentration phosphorus (P) or arsenic (As) in case of an N-MOS transistor, or by implanting a P-type impurity such as a low-concentration boron B or BF2 in case of a P-MOS transistor. Then a silicon oxide layer is deposited all over the substrate by LPCVD, and the silicon oxide layer is etched back by anisotropic dry etching, to thereby form a sidewall 10 on a lateral face of the gate electrode 9 as shown in FIG. FIG. 10C.
After the above, as shown in FIG. 10D, a source/drain region 4 is formed by implanting an N-type impurity such as a high-concentration P or As in case of an N-MOS transistor, or by implanting a P-type impurity such as a high-concentration B or BF2 in case of a P-MOS transistor, utilizing the gate electrode 9 and the sidewall 10 as a mask. At this stage, the LDD region 7 that serves as an offset gate layer and the high-concentration source/drain region 4 are formed in a self-aligned manner, right under the sidewall 10 and outside thereof respectively.
Referring to such MOS transistor, when forming a shallow source/drain region in the proximity of a substrate surface, a sheet resistance of an impurity diffusion layer tends to increase. Accordingly, as a popular method of reducing such resistance a silicide layer which is a compound of silicon and a metal is formed in a part of the impurity diffusion layer. However, since the silicide layer is formed through a reaction of silicon and a metal, it is difficult to accurately control a thickness of the silicide layer. Consequently, once the silicide layer has grown in an excessive thickness, leakage is prone to take place between the substrate. Also, in case of such MOS transistor, forming a shallow source/drain region in the proximity of the substrate surface often incurs leakage at a junction, because impurity concentration in the source/drain region shows a steep gradient in a depth wise direction.
The JP-A No. 1995-131006 discloses a structure and method whereby junction leakage between a source/drain region bottom portion and a semiconductor substrate is reduced, while restraining a short channel effect in an N-MOS transistor provided with a shallow source/drain region in the proximity of the substrate surface.
FIGS. 11A to 11C are cross-sectional process drawings showing a method of manufacturing a conventional N-MOS transistor.
This document describes a method of implanting an N-type impurity such as As utilizing the gate electrode 9 as a mask to form an N-type impurity layer 12 on a P-type semiconductor substrate 1 as shown in FIG. 11A; likewise implanting an N-type impurity such as P utilizing the gate electrode 9 as a mask to form a low-concentration N-type impurity layer 13 only on a bottom portion of the N-type impurity layer 12 as shown in FIG. 11B; then executing a brief heat treatment so as to form the N-type source/drain region 4 having a mild ion concentration gradient as shown in FIG. 1C.